The invention relates generally to a semiconductor device and, more particularly, to a method for manufacturing a non-volatile memory device having a charge trap layer.
Non-volatile memory devices are electrically programmable and erasable memory devices and are widely used in electronic components which require information to be maintained even when the power is not supplied. The non-volatile memory devices may be formed having a floating gate structure and information may be programmed or erased by injecting or removing a charge in the floating gate. As the degree of integration of memory devices increases, there has been suggested a non-volatile memory device structure in which a charge is injected or removed in a charge trap layer.
In a non-volatile memory device having the charge trap layer, the charge trap layer and a blocking layer are formed on a tunneling layer formed on a semiconductor substrate and a control gate is formed on the blocking layer. Such a non-volatile memory device having the charge trap layer is suggested as a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) structure or a Metal-Aluminum Nitride-Oxide-Semiconductor (MANOS) structure depending on properties of a layer formed on the tunneling layer. A charge is stored in and discharged from the charge trap layer to carry out electrically programming and erasing operations depending on a bias applied to the non-volatile memory device formed in such a structure.
Since the injection and removal of charge carriers such as electrons and holes into or from the trap layer is carried out through the underlying tunneling layer, the behavior thereof may vary with the structure of the tunneling layer. In order to improve the tunneling operation, efforts to increase an effective dielectric constant of the tunneling layer may be considered. One of these efforts is to form the tunneling layer in a multilayer structure including a layer of a high dielectric material. However, an undesired interfacial layer having low dielectric constant, e.g. a silicate layer or a silicide layer may be excessively generated in interface between the layers in the multilayer structure. This interfacial layer of low dielectric constant may lead to reduction in total effective dielectric constant of the tunneling layer, and generation of the interfacial layer may cause undesirable, excessively increased roughness of the layers. Therefore, the properties of entire tunneling layer as well as operation properties of the memory cell may deteriorate.